GS2961 Datasheet, PDF (31/104 Pages) Gennum Corporation – 3Gb/s, HD, SD SDI Receiver, with Integrated Adaptive Cable Equalizer complete with SMPTE Video Processing

• A coarse frequency acquisition loop sets the centre frequency of the integrated
Voltage Controlled Oscillator (VCO) using an external 27MHz reference clock
• A fine frequency and phase locked loop aligns the VCO’s phase and frequency to
the input serial digital stream
The frequency lock loop results in a very fast lock time.
The sampling stage re-times the serial digital input with the locked VCO clock. This
generates a clean serial digital stream, which may be output on the SDO/SDO output
pins and converted to parallel data for further processing. Parallel data is not affected by
RC_BYP. Only the SDO is affected by this pin.
4.5.1 PLL Loop Bandwidth
The fine frequency and phase lock loop in the GS2961 reclocker is non-linear. The PLL
loop bandwidth scales with the jitter amplitude of the input data stream; automatically
reduces bandwidth in response to higher jitter. This allows the PLL to reject more of the
jitter in the input data stream and produce a very clean reclocked output.
The loop bandwidth of the GS2961 PLL is defined with 0.2UI input jitter. The bandwidth
is controlled by the LB_CONT pin. Under nominal conditions, with the LB_CONT pin
floating and 0.2UI input jitter applied, the loop bandwidth is set to 1/1000 of the
frequency of the input data stream. Connecting the LB_CONT pin to 3.3V reduces the
bandwidth to half of the nominal setting. Connecting the LB_CONT pin to GND increases
the bandwidth to double the nominal setting. Table 4-2 below summarizes this
information.
Table 4-2: PLL Loop Bandwidth
Input Data Rate
LB_CONT Pin Connection
SD
3.3V
Floating
0V
HD
3.3V
Floating
0V
3G
3.3V
Floating
0V
1_{Measured with 0.2UI input jitter applied}
Loop Bandwidth (MHz)¹
0.135
0.27
0.54
0.75
1.5
3.0
1.5
3.0
6.0
GS2961 3Gb/s, HD, SD SDI Receiver, with Integrated
Adaptive Cable Equalizer
Data Sheet
48004 - 2
November 2009
31 of 104