GS2961 Datasheet, PDF (12/104 Pages) Gennum Corporation – 3Gb/s, HD, SD SDI Receiver, with Integrated Adaptive Cable Equalizer complete with SMPTE Video Processing

Table 1-1: Pin Descriptions (Continued)
Pin
Number
F1, G1
Name
Timing
AGCP, AGCN
Type
F7
CS_TMS
Input
F8
SCLK_TCK
Input
F9, F10, H9,
H10, J8, J9,
J10, K8, K9,
K10
DOUT8, 9, 6, 7, 1,
4, 5, 0, 2, 3
Output
G3
RC_BYP
Input
Description
Automatic Gain Control for the equalizer. Attach the AGC capacitor
between these pins.
COMMUNICATION SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Chip select / test mode start.
In JTAG mode (JTAG/HOST = HIGH), this pin is Test Mode Start, used
to control the operation of the JTAG test.
In host interface mode (JTAG/HOST = LOW), this pin operates as the
host interface chip select and is active LOW.
COMMUNICATION SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Serial data clock signal.
In JTAG mode (JTAG/HOST = HIGH), this pin is the JTAG clock.
In host interface mode (JTAG/HOST = LOW), this pin is the host
interface serial bit clock.
All JTAG/host interface addresses and data are shifted into/out of
the device synchronously with this clock.
PARALLEL DATA BUS
Signal levels are LVCMOS/LVTTL compatible.
20-bit mode
20bit/10bit = HIGH
SMPTE mode (SMPTE_BYPASS = HIGH
and DVB_ASI = LOW):
Chroma data output for SD and HD
data rates; Data Stream 2 for 3G data
rate
DVB-ASI mode (SMPTE_BYPASS = LOW
and DVB_ASI = HIGH):
Not defined
Data-Through mode (SMPTE_BYPASS =
LOW and DVB_ASI = LOW):
Data output
10-bit mode
20bit/10bit = LOW
Forced LOW
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
When this pin is LOW, the serial digital output is the buffered
version of the input serial data. When this pin is HIGH, the serial
digital output is the reclocked version of the input serial data.
GS2961 3Gb/s, HD, SD SDI Receiver, with Integrated
Adaptive Cable Equalizer
Data Sheet
48004 - 2
November 2009
12 of 104