GS2961 Datasheet, PDF (7/104 Pages) Gennum Corporation – 3Gb/s, HD, SD SDI Receiver, with Integrated Adaptive Cable Equalizer complete with SMPTE Video Processing

Figure 4-34: GSPI Application Interface Connection ........................................................................ 78
Figure 4-35: Command Word Format ..................................................................................................... 78
Figure 4-36: Data Word Format ................................................................................................................ 79
Figure 4-37: Write Mode .............................................................................................................................. 80
Figure 4-38: Read Mode ............................................................................................................................... 80
Figure 4-39: GSPI Time Delay .................................................................................................................... 80
Figure 4-40: In-Circuit JTAG ...................................................................................................................... 95
Figure 4-41: System JTAG ........................................................................................................................... 96
Figure 4-42: Reset Pulse ............................................................................................................................... 97
Figure 7-1: Pb-free Solder Reflow Profile ............................................................................................ 103
List of Tables
Table 1-1: Pin Descriptions ............................................................................................................................ 8
Table 2-1: Absolute Maximum Ratings................................................................................................... 15
Table 2-2: Recommended Operating Conditions................................................................................ 15
Table 2-3: DC Electrical Characteristics ................................................................................................. 16
Table 2-4: AC Electrical Characteristics ................................................................................................. 18
Table 4-1: Serial Digital Output................................................................................................................. 30
Table 4-2: PLL Loop Bandwidth ................................................................................................................ 31
Table 4-3: Input Clock Requirements...................................................................................................... 32
Table 4-4: Lock Detect Conditions............................................................................................................ 33
Table 4-5: GS2961 Output Video Data Format Selections................................................................ 37
Table 4-6: GS2961 PCLK Output Rates ................................................................................................... 39
Table 4-7: Switch Line Position for Digital Systems ........................................................................... 44
Table 4-8: Output Signals Available on Programmable Multi-Function Pins............................ 46
Table 4-9: Supported CEA-861 Formats................................................................................................. 49
Table 4-10: CEA861 Timing Formats ....................................................................................................... 50
Table 4-11: Supported Video Standard Codes ..................................................................................... 57
Table 4-12: Data Format Register Codes ................................................................................................ 60
Table 4-13: Error Status Register and Error Mask Register .............................................................. 62
Table 4-14: SMPTE 352M Packet Data .................................................................................................... 68
Table 4-15: IOPROC_DISABLE Register Bits......................................................................................... 70
Table 4-16: GSPI Time Delay...................................................................................................................... 80
Table 4-17: GSPI Timing Parameters (50% levels; 3.3V or 1.8V operation) ................................ 81
Table 4-18: Configuration and Status Registers................................................................................... 82
Table 4-19: ANC Extraction FIFO Access Registers............................................................................ 94
Table 7-1: Packaging Data......................................................................................................................... 102
GS2961 3Gb/s, HD, SD SDI Receiver, with Integrated
Adaptive Cable Equalizer
Data Sheet
48004 - 2
November 2009
7 of 104