GS2961 Datasheet, PDF (35/104 Pages) Gennum Corporation – 3Gb/s, HD, SD SDI Receiver, with Integrated Adaptive Cable Equalizer complete with SMPTE Video Processing

4.9 Parallel Data Outputs
The parallel data outputs are aligned to the rising edge of the PCLK.
4.9.1 Parallel Data Bus Buffers
The parallel data bus, status signal outputs and control signal input pins are all
connected to high-impedance buffers.
The device supports 1.8 or 3.3V (LVTTL and LVCMOS levels) supplied at the IO_VDD and
IO_GND pins.
All output buffers (including the PCLK output), are set to high-impedance in Reset mode
(RESET_TRST = LOW).
I/O Timing Specs:
10-bit SDR Mode:
6.734ns (HD 10-bit)
37.037ns (SD 10-bit)
DBUS[19:10]
Y0
Cr0
Y1
Cb1
PCLK_OUT
toh
tod
80%
20%
tr
80%
20%
tf
dbus
stat
toh
1.000ns
1.000ns
tr/tf (min)
0.400ns
0.500ns
3.3V
Cload
tod
6 pF
3.700ns
4.100ns
tr/tf (max)
1.400ns
1.600ns
10bHD Mode
Cload
15 pF
toh
1.000ns
1.000ns
tr/tf (min)
0.400ns
0.400ns
1.8V
Cload
tod
6 pF
3.700ns
4.400ns
tr/tf (max)
1.400ns
1.500ns
Cload
15 pF
dbus
stat
toh tr/tf (min)
19.400ns 0.400ns
19.400ns 0.500ns
3.3V
Cload
tod tr/tf (max)
6 pF
22.200ns 1.400ns
22.200ns 1.600ns
10bSD Mode
Cload
15 pF
toh tr/tf (min)
19.400ns 0.400ns
19.400ns 0.400ns
1.8V
Cload
tod tr/tf (max)
6 pF
22.200ns 1.400ns
22.200ns 1.500ns
Cload
15 pF
Figure 4-5: PCLK to Data and Control Signal Output Timing - SDR Mode 1
GS2961 3Gb/s, HD, SD SDI Receiver, with Integrated
Adaptive Cable Equalizer
Data Sheet
48004 - 2
November 2009
35 of 104