GS2961 Datasheet, PDF (11/104 Pages) Gennum Corporation – 3Gb/s, HD, SD SDI Receiver, with Integrated Adaptive Cable Equalizer complete with SMPTE Video Processing

Table 1-1: Pin Descriptions (Continued)
Pin
Number
C7
D4, E4, F4
D5, E5, F5,
G4, G5, H3
D6, E6, F6,
G6
D7
D8
E1
E2
E7
E8
Name
Timing
Type
Description
RESET_TRST
PLL_GND
CORE_GND
CORE_VDD
SW_EN
JTAG/HOST
EQ_VDD
EQ_GND
SDOUT_TDO
SDIN_TDI
Input
Input Power
Input Power
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to reset the internal operating conditions to default settings
and to reset the JTAG sequence.
Normal mode (JTAG/HOST = LOW):
When LOW, all functional blocks are set to default conditions and
all digital output signals become high impedance.
When HIGH, normal operation of the device resumes.
JTAG test mode (JTAG/HOST = HIGH):
When LOW, all functional blocks are set to default and the JTAG test
sequence is reset.
When HIGH, normal operation of the JTAG test sequence resumes
after RESET_TRST is de-asserted.
GND pins for the Reclocker PLL. Connect to analog GND.
GND connection for device core. Connect to digital GND.
Input Power POWER connection for device core. Connect to 1.2V DC digital.
Input
Input
Input Power
Input Power
Output
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to enable switch-line locking, as described in Section 4.10.1.
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to select JTAG test mode or host interface mode.
When JTAG/HOST is HIGH, the host interface port is configured for
JTAG test.
When JTAG/HOST is LOW, normal operation of the host interface
port resumes.
POWER pin for SDI buffer. Connect to 3.3V DC analog.
GND pin for SDI buffer. Connect to analog GND.
COMMUNICATION SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
GSPI serial data output/test data out.
In JTAG mode (JTAG/HOST = HIGH), this pin is used to shift test
results from the device.
In host interface mode, this pin is used to read status and
configuration data from the device.
COMMUNICATION SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
GSPI serial data in/test data in.
In JTAG mode (JTAG/HOST = HIGH), this pin is used to shift test data
into the device.
In host interface mode, this pin is used to write address and
configuration data words into the device.
GS2961 3Gb/s, HD, SD SDI Receiver, with Integrated
Adaptive Cable Equalizer
Data Sheet
48004 - 2
November 2009
11 of 104