GS2961 Datasheet, PDF (71/104 Pages) Gennum Corporation – 3Gb/s, HD, SD SDI Receiver, with Integrated Adaptive Cable Equalizer complete with SMPTE Video Processing

4.18.2 Line Based CRC Correction & Insertion
When CRC Error Correction and Insertion is enabled, the GS2961 generates and inserts
line based CRC words into both the Y and C channels of the data stream.
Line based CRC word generation and insertion only occurs in HD and 3G modes, and is
enabled in when the IOPROC_EN/DIS pin is HIGH and the CRC_INS_DSX_MASK bit in
the IOPROC_X register is set LOW.
4.18.3 Line Number Error Correction & Insertion
When Line Number Error Correction and Insertion is enabled, the GS2961 calculates
and inserts line numbers into the output data stream. Re-calculated line numbers are
inserted into both the Y and C channels.
Line number generation is in accordance with the relevant HD or 3G video standard as
determined by the Automatic Standards Detection block.
This feature is enabled when the device is operating in HD or 3G modes, the
IOPROC_EN/DIS pin is HIGH and the LNUM_INS_DSX_MASK bit in the IOPROC_X
register is set LOW.
4.18.4 ANC Data Checksum Error Correction & Insertion
When ANC data Checksum Error Correction and Insertion is enabled, the GS2961
generates and inserts ancillary data checksums for all ancillary data words by default.
Where user specified ancillary data has been programmed (see Section 4.17.1), only the
checksums for the programmed ancillary data are corrected.
This feature is enabled when the IOPROC_EN/DIS pin is HIGH and the
ANC_CHECKSUM_INSERTION_DSX_MASK bit in the IOPROC_X register is set LOW.
4.18.5 EDH CRC Correction & Insertion
When EDH CRC Error Correction and Insertion is enabled, the GS2961 generates and
overwrites full field and active picture CRC check-words.
Additionally, the device sets the active picture and full field CRC 'V' bits HIGH in the
EDH packet. The AP_CRC_V and FF_CRC_V register bits only report the received EDH
validity flags.
EDH FF and AP CRC's are only inserted when the device is operating in SD mode, and if
the EDH data packet is detected in the received video data.
Although the GS2961 modifies and inserts EDH CRC's and EDH packet checksums, EDH
error flags are only updated when the EDH_FLAG_UPDATE_MASK bit is LOW.
This feature is enabled in SD mode, when the IOPROC_EN/DIS pin is HIGH and the
EDH_CRC_INS_MASK bit in the IOPROC_1 register is set LOW.
GS2961 3Gb/s, HD, SD SDI Receiver, with Integrated
Adaptive Cable Equalizer
Data Sheet
48004 - 2
November 2009
71 of 104