GS2961 Datasheet, PDF (65/104 Pages) Gennum Corporation – 3Gb/s, HD, SD SDI Receiver, with Integrated Adaptive Cable Equalizer complete with SMPTE Video Processing

For 3G signals, ancillary data may be placed in either or both of the virtual interface data
streams. Both data streams are examined for ancillary data.
For a 3G data stream formatted as per Level A mapping:
• The ancillary data is placed in Data Stream 1 first, with overflow into Data Stream 2
• SMPTE 352M packets are duplicated in both data streams
For a 3G data stream formatted as per Level B mapping:
• Each multiplexed data stream forming the 3G signal contains ancillary data
embedded according to SMPTE 291M
• Each multiplexed data stream forming the 3G signal contains SMPTE 352M packets
embedded according to SMPTE 425M
When operating in HD mode, the Y/1ANC signal is HIGH whenever ancillary data is
detected in the Luma data stream, and C/2ANC is HIGH whenever ancillary data is
detected in the Chroma data stream. The signals are asserted HIGH at the start of the
ancillary data preamble, and remain HIGH until after the ancillary data checksum.
When detecting ancillary data in 3G Level A data, the Y/1ANC status output is HIGH
whenever Data Stream 1 ancillary data is detected and the C/2ANC status output is
HIGH whenever Data Stream 2 ancillary data is detected.
When detecting ancillary data in 3G Level B data, the Y/1ANC status output is HIGH
whenever Data Stream 1 ancillary data is detected on either Y or C channels and the
C/2ANC status output is HIGH whenever Data Stream 2 ancillary data is detected on
either Y or C channels.
When operating in SD mode, the Y/1ANC and C/2ANC signals depend on the output
data format. For 20-bit demultiplexed data, the Y/1ANC and C/2ANC signals operate
independently to indicate the first and last ancillary Data Word position in the Luma
and/or Chroma data streams. For 10-bit multiplexed data, the Y/1ANC signal is HIGH
whenever ancillary data is detected, and the C/2ANC signal is always LOW.
When operating in 3G modes, the Y/1ANC and C/2ANC flags are both zero if the 10-bit
multiplexed output format is selected.
These status signal outputs are synchronous with PCLK and may be used as
clock-enables for external logic, or as write-enables for an external FIFO or other
memory devices.
The operation of the Y/1ANC and C/2ANC signals is shown below in Figure 4-29.
NOTE 1: When I/O processing is disabled, the Y/1ANC and C/2ANC flags may toggle, but
they are invalid and should be ignored.
NOTE 2: In 3G Level B mode, if the ANC_EXT_SEL_DS2_DS1 bit is HIGH and the
ANC_DATA_DELETE bit is HIGH, the Y/1ANC and C/2ANC flags are not valid.
NOTE3: For 3G Level B data, the Y/1ANC flag identifies all ANC data on Data Stream 1
(Link A), whether it is embedded in the Y or C component – ANC data is not identified
separately for each component. Similarly, the C/2ANC flag identifies all ANC data on
Data Stream 2 (Link B), whether it is embedded in the Y or C component.
GS2961 3Gb/s, HD, SD SDI Receiver, with Integrated
Adaptive Cable Equalizer
Data Sheet
48004 - 2
November 2009
65 of 104