GS2961 Datasheet, PDF (30/104 Pages) Gennum Corporation – 3Gb/s, HD, SD SDI Receiver, with Integrated Adaptive Cable Equalizer complete with SMPTE Video Processing

SDI
SDI
GAIN_SEL
Equalizer
AGC
DC
Restore
Output
SDO
SDO
AGC AGC
Figure 4-3: GS2961 Integrated EQ Block Diagram
4.4 Serial Digital Loop-Through Output
The GS2961 contains a 100Ω differential serial output buffer which can be configured to
output either a retimed or a buffered version of the serial digital input. The SDO and SDO
outputs of this buffer can interface directly to a 3Gb/s-capable, SMPTE compliant
Gennum cable driver. See 5.3 Typical Application Circuit on page 99.
When the RC_BYP pin is set HIGH, the serial digital output is the re-timed version of the
serial input.
When the RC_BYP pin is set LOW, the serial digital output is simply the buffered version
of the serial input, bypassing the internal reclocker.
The output can be disabled by setting the SDO_EN/DIS pin LOW. The output is also
disabled when the STANDBY pin is asserted HIGH. When the output is disabled, both
SDO and SDO pins are set to VDD and remain static.
The SDO output is muted when the RC_BYP pin is set HIGH and the PLL is unlocked
(LOCKED pin is LOW). When muted, the output is held static at logic ‘0’ or logic ‘1’.
Table 4-1: Serial Digital Output
SDO_EN/DIS
0
1
1
RC_BYP
X
1
0
SDO/SDO
Disabled
Re-timed
Buffered (not re-timed)
NOTE: the serial digital output is muted when the GS2961 is unlocked.
4.5 Serial Digital Reclocker
The GS2961 includes both a PLL stage and a sampling stage.
The PLL is comprised of two distinct loops:
GS2961 3Gb/s, HD, SD SDI Receiver, with Integrated
Adaptive Cable Equalizer
Data Sheet
48004 - 2
November 2009
30 of 104