GS2961 Datasheet, PDF (13/104 Pages) Gennum Corporation – 3Gb/s, HD, SD SDI Receiver, with Integrated Adaptive Cable Equalizer complete with SMPTE Video Processing

Table 1-1: Pin Descriptions (Continued)
Pin
Number
G7
G8
H1
H2
H5
H6
H7
Name
Timing
Type
Description
SMPTE_BYPASS
DVB_ASI
BUFF_VDD
BUFF_GND
TIM_861
XTAL_OUT
20bit/10bit
Input/Output
CONTROL SIGNAL INPUT/OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Indicates the presence of valid SMPTE data.
When the AUTO/MAN bit in the host interface register is HIGH
(Default), this pin is an OUTPUT. SMPTE_BYPASS is HIGH when the
device locks to a SMPTE compliant input. SMPTE_BYPASS is LOW
under all other conditions.
When the AUTO/MAN bit in the host interface register is LOW, this
pin is an INPUT:
No SMPTE scrambling takes place, and none of the I/O processing
features of the device are available when SMPTE_BYPASS is set
LOW.
When SMPTE_BYPASS is set HIGH, the device carries out SMPTE
scrambling and I/O processing.
When SMPTE_BYPASS and DVB_ASI are both set LOW, the device
operates in Data-Through mode.
Input/Output
CONTROL SIGNAL INPUT
Signal Levels are LVCMOS/LVTTL compatible.
Used to enable/disable DVB-ASI data extraction in manual mode.
When the AUTO/MAN bit in the host interface is LOW, this pin is an
input and when the DVB_ASI pin is set HIGH the device will carry out
DVB_ASI data extraction and processing. The SMPTE_BYPASS pin
must be set LOW. When SMPTE_BYPASS and DVB_ASI are both set
LOW, the device operates in Data-Through mode.
When the AUTO/MAN bit in the host interface is HIGH (default),
DVB-ASI is configured as a status output (set LOW), and DVB-ASI
input streams are not supported or recognized.
Input Power POWER pin for the serial digital output 50Ω buffer. Connect to 3.3V
DC analog.
Input Power GND pin for the cable driver buffer. Connect to analog GND.
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to select CEA-861 timing mode.
When TIM_861 is HIGH, the device outputs CEA 861 timing signals
(HSYNC/VSYNC/DE) instead of H:V:F digital timing signals.
Digital
Output
Buffered 27MHz crystal output. Can be used to cascade the crystal
signal.
Input
CONTROL SIGNAL INPUT
Levels are LVCMOS/LVTTL compatible.
Used to select the output bus width.
HIGH = 20-bit, LOW = 10-bit.
GS2961 3Gb/s, HD, SD SDI Receiver, with Integrated
Adaptive Cable Equalizer
Data Sheet
48004 - 2
November 2009
13 of 104