GS2961 Datasheet, PDF (14/104 Pages) Gennum Corporation – 3Gb/s, HD, SD SDI Receiver, with Integrated Adaptive Cable Equalizer complete with SMPTE Video Processing

Table 1-1: Pin Descriptions (Continued)
Pin
Number
H8
J1, K1
J2
J6, K6
K2
Name
Timing
Type
Description
IOPROC_EN/DIS
SDO, SDO
SDO_EN/DIS
XTAL2, XTAL1
STANDBY
Input
CONTROL SIGNAL INPUT
Levels are LVCMOS/LVTTL compatible.
Used to enable or disable video processing features. When
IOPROC_EN is HIGH, the video processing features of the device are
enabled. When IOPROC_EN is LOW, the processing features of the
device are disabled, and the device is in a low-latency operating
mode.
Output
Serial Data Output Signal.
50Ω CML buffer for interfacing to an external cable driver.
Serial digital output signal operating at 2.97Gb/s, 2.97/1.001Gb/s,
1.485Gb/s, 1.485/1.001Gb/s and 270Mb/s.
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to enable/disable the serial digital output stage.
When SDO_EN/DIS is LOW, the serial digital output signals, SDO and
SDO, are both pulled HIGH.
When SDO_EN/DIS is HIGH, the serial digital output signals, SDO and
SDO, are enabled.
Analog Input Input connection for 27MHz crystal.
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
When this pin is set HIGH, the device is placed in a power-saving
mode. No data processing occurs, and the digital I/Os are powered
down.
In this mode, the serial digital output signals, SDO and SDO, are
both pulled HIGH.
GS2961 3Gb/s, HD, SD SDI Receiver, with Integrated
Adaptive Cable Equalizer
Data Sheet
48004 - 2
November 2009
14 of 104