GS2961 Datasheet, PDF (48/104 Pages) Gennum Corporation – 3Gb/s, HD, SD SDI Receiver, with Integrated Adaptive Cable Equalizer complete with SMPTE Video Processing

PCLK (DDR)
MULTIPLEXED LINKA/LINKB DATA
H
V
F
PCLK (DDR)
MULTIPLEXED LINKA/LINKB DATA
H
V
F
3FF
3FF 3FF
3FF 000 000 000 000 000 000 000 000
XYZ
(eav)
XYZ
(eav)
XYZ
(eav)
XYZ
(eav)
H VF T IM IN G A T E A V
3FF 3FF
3FF 3FF
000 000 000 000 000 000 000 000
XYZ
(sav)
XYZ
(sav )
XYZ
(sav )
XYZ
(sav )
H VF T IM IN G A T S A V
H S IG N A L T IM IN G :
H _C O N F IG = LO W
H _C O N F IG = H IG H
Figure 4-13: H:V:F Output Timing - 3G Level B 10-bit Mode
PC LK
LU M A D A T A IN P U T
C H R O M A D A T A IN P U T
H
V
F
3FF
000
3FF
000
H S IG N A L T IM IN G :
000
000
X Y Z (EAV)
X Y Z (EAV)
H _C O N F IG = LO W
3FF
000
3FF
000
H _C O N F IG = H IG H
Figure 4-14: H:V:F Output Timing - HD 20-bit Output Mode
000
000
X Y Z (SAV)
X Y Z (SAV)
PC LK
M U L T IP LE X E D Y 'C bC r D A T A IN P U T
H
V
F
PC LK
M U L T IP LE X E D Y 'C bC r D A T A IN P U T
H
V
F
3FF
3FF
000
000
000
0 0 0 X Y Z (EAV) X Y Z (EAV)
H V F T IM IN G A T E A V
3FF
3FF
000
000
000
000
X Y Z (SAV) X Y Z (SAV)
H V F T IM IN G A T S A V
Figure 4-15: H:V:F Output Timing - HD 10-bit Output Mode
PCLK
C H R O M A D A T A IN P U T
LU M A D ATA IN P U T
H
V
F
3FF
000
000
X Y Z (EAV)
H S IG N A L T IM IN G :
H _C O N F IG = LO W
3FF
000
000
X Y Z (SAV)
H _C O N F IG = H IG H
Figure 4-16: H:V:F Output Timing - SD 20-bit Output Mode
PC LK
M U L T IP LE X E D Y 'C b C r D A T A IN P U T
H
V
F
3FF
000
H S IG N A L T IM IN G :
0 0 0 X Y Z (EAV)
H _C O N F IG = LO W
3FF
000
000
X Y Z (SAV)
H _C O N F IG = H IG H
Figure 4-17: H:V:F Output Timing - SD 10-bit Output Mode
GS2961 3Gb/s, HD, SD SDI Receiver, with Integrated
Adaptive Cable Equalizer
Data Sheet
48004 - 2
November 2009
48 of 104