GS2961 Datasheet, PDF (49/104 Pages) Gennum Corporation – 3Gb/s, HD, SD SDI Receiver, with Integrated Adaptive Cable Equalizer complete with SMPTE Video Processing

4.12.1 CEA-861 Timing Generation
The GS2961 is capable of generating CEA 861 timing instead of SMPTE HVF timing for
all of the supported video formats.
This mode is selected when the TIM_861 pin is HIGH.
Horizontal sync (HSYNC), Vertical sync (VSYNC), and Data Enable (DE) timing are
output on the STAT[2:0] pins by default.
Table 4-9 shows the CEA-861 formats supported by the GS2961:
Table 4-9: Supported CEA-861 Formats
Format
CEA-861 Format
720(1440) x 480i @ 59.94/60Hz
6&7
720(1440) x 576i @ 50Hz
21 & 22
1280 x 720p @ 59.94/60Hz
4
1280 x 720p @ 50Hz
19
1920 x 1080i @ 59.94/60Hz
5
1920 x 1080i @ 50Hz
20
1920 x 1080p @ 29.97/30Hz
34¹
1920 x 1080p @ 25Hz
33²
1920 x 1080p @ 23.98/24Hz
32
1920 x 1080p @ 59.94/60Hz
16¹
1920 x 1080p @ 50Hz
31²
NOTES:
1,2: Timing is identical for the corresponding formats.
VD_STD[5:0]
16h, 17h, 19h, 1Bh
18h, 1Ah
20h, 00h
24h, 04h
2Ah, 0Ah
2Ch, 0Ch
2Bh, 0Bh
2Dh, 0Dh
30h, 10h
2Bh
2Dh
4.12.1.1 Vertical Timing
When CEA861 timing is selected, the device outputs standards compliant CEA861
timing signals as shown in the figures below; for example 240 active lines per field for
SMPTE 125M.
The register bit TRS_861 is used to select DFP timing generator mode which follows the
vertical blanking timing as defined by the embedded TRS code words. This setting is
helpful for 525i. When TRS_861 is set LOW, DE will go HIGH for 480 lines out of 525.
When TRS_861 is set HIGH, DE will go HIGH for 487 lines out of 525.
The timing of the CEA 861 timing reference signals can be found in the CEA 861
specificaitons. For information, they are included in the following diagrams. These
diagrams may not be comprehensive.
GS2961 3Gb/s, HD, SD SDI Receiver, with Integrated
Adaptive Cable Equalizer
Data Sheet
48004 - 2
November 2009
49 of 104