GS2961 Datasheet, PDF (41/104 Pages) Gennum Corporation – 3Gb/s, HD, SD SDI Receiver, with Integrated Adaptive Cable Equalizer complete with SMPTE Video Processing

Bits[4:0] (DEL_LINE_OFFSET) comprise a fine delay adjustment to shift the PCLK in
40ps increments (typical conditions). The maximum fine delay adjustment is
approximately 1.2ns under nominal conditions.
An example delay adjustment over min/typ/max conditions is illustrated in Figure 4-9.
The target delay is 0.84 ns under typical conditions (approximately 45º PCLK phase
shift), and requires a control word setting of 0x0014 for address 0x006C.
PCLK
90º phase shift
3.367ns
6.734ns
1.684ns
0.842ns
PCLK
(MIN)
PCLK
Ranges: _(TYP)
PCLK
(MAX)
Typical 45º phase shift
3.367ns
6.734ns
1.684ns
Figure 4-9: Delay Adjustment Ranges
4.10 Timing Signal Generator
The GS2961 has an internal timing signal generator which is used to generate digital
FVH timing reference signals, to detect and correct certain error conditions and
automatic video standard detection.
The timing signal generator is only operational in SMPTE mode (SMPTE_BYPASS =
HIGH).
The timing signal generator consists of a number of counters and comparators operating
at video pixel and video line rates. These counters maintain information about the total
line length, active line length, total number of lines per field/frame and total active lines
per field/frame for the received video standard.
It takes one video frame to obtain full synchronization to the received video standard.
offset [5] = 1 (90º phase shift)
0.58ns
delay
0.84ns
delay
1.38ns
delay
GS2961 3Gb/s, HD, SD SDI Receiver, with Integrated
Adaptive Cable Equalizer
Data Sheet
48004 - 2
November 2009
41 of 104