GS4901B Datasheet, PDF (85/95 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

GS4901B/GS4900B Preliminary Data Sheet
Table 3-13: Configuration and Status Registers (Continued)
Register Name
Address Bit
Description
R/W Default
V_Stop_4
Operator_Polarity_4
Ext_Audio_Mode
69h
15
Reserved. Set this bit to zero when writing to 69h.
–
–
69h
14-0
The value programmed in this register indicates the end R/W
0
line number of the trailing edge of the user-programmed
V Sync signal USER4_V. For interlaced output
standards, this value corresponds to the odd field line
number.
NOTE: The value programmed in this register must not
exceed the maximum number of lines per field of the
outgoing standard.
Reference: Section 3.8.3 on page 59
6Ah
15-4
Reserved. Set these bits to zero when writing to 6Ah. –
–
6Ah
3
Polarity_4 - Use this bit to invert the polarity of the final R/W
1
USER4 signal.
By default, the polarity of the user programmed signals
is active LOW. The polarity may be switched to active
HIGH by setting this bit LOW.
Reference: Section 3.8.3 on page 59
6Ah
2
AND_4 - logical operator: USER4_H AND USER4_V R/W
0
Set this bit HIGH to output a signal that is only active
when both USER4_H and USER4_V are active.
When this bit is HIGH, bit 1 and bit 0 of this register will
be ignored.
Reference: Section 3.8.3 on page 59
6Ah
1
OR_4 - logical operator: USER4_H OR USER4_V
R/W
0
Set this bit HIGH to output a signal that is active
whenever USER4_H or USER4_V are active.
When this bit is HIGH bit 0 of this register will be
ignored.
Reference: Section 3.8.3 on page 59
6Ah
0
XOR_4 - logical operator: USER4_H XOR USER4_V R/W
0
Set this bit HIGH to output a signal with the following
attributes: Signal becomes active when either
USER4_H or USER4_V is active. Signal is inactive
when USER4_H and USER4_V are both active or both
inactive.
Reference: Section 3.8.3 on page 59
81h
15-0
Set this register to 20C1h to enable the Extended Audio R/W
0
Mode of the device.
To fully enable this mode, VID_STD[5:0] must be set to
4d, and the F_Lock_Mask and V_Lock_Mask bits [4:3]
of register address 16h must be set to 1.
NOTE: Once this register is programmed, it must be
updated using bit 6 of register 16h.
Reference: Section 3.9 on page 62
37703 - 0 April 2006
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