GS4901B Datasheet, PDF (37/95 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

GS4901B/GS4900B Preliminary Data Sheet
3. When locking the 525-line SD output standards to the “f/1.001” HD input
reference standards, the device will delay all line-based output timing signals
by ΔVSync lines relative to the input VSYNC reference. This will occur even
when the V_Offset register is not programmed. The user may compensate for
this delay by subtracting ΔVSync lines from the desired vertical offset before
loading this value into the register.
The value ΔVSync is given by the equation:
ΔVSync = HSYNC_IN_Period + ΔVSYNC_HSYNC – (2 × HSYNC_OUT_Period )
where:
HSYNC_IN_Period = the period of the H reference pulse
ΔVSYNC_HSYNC = the time difference between the leading edges of the
applied V and H reference pulses
Hsync_OUT_Period = the period of the generated H Sync output
See Figure 3-1. H_Feedback_Divide represents the numerator of the ratio of
the output clock frequency to the frequency of the H reference pulse.
HSYNC
HSYNC_IN_Period
VSYNC
H Sync
Δ VSYNC_HSYNC
HSync_OUT_Period
V Sync
Δ VSync
Figure 3-1: SD-HD Calculation
4. For sync-based input references, the device will advance all line-based output
timing signals by 1 line if the value programmed in the H_Offset register is
greater than 20. The user may compensate for this advance by adding 1 line
to the desired vertical offset before loading this value into the register. In
addition, the internal V_lock and F_lock signals reported in bits 3 and 4 of
register 16h will be LOW when H_Offset = 21 only, although the device will
remained genlocked. The user may choose to mask these lock signals such
that the device will continue to report genlock under this condition.
37703 - 0 April 2006
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