GS4901B Datasheet, PDF (26/95 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

GS4901B/GS4900B Preliminary Data Sheet
Table 1-3: Output Timing Signals (Continued)
Signal Name
Description
Default Output Pin
10 Field Identification
Display Enable
Audio Frame Sync
(GS4901B only)
The 10 Field Identification (10FID) signal is used to indicate the 10-field
sequence for 29.97Hz, 30Hz, 59.94Hz and 60Hz video standards. It will be
LOW for output standards with other frame rates.
TIMING_OUT_7
The sequence defines the phase relationship between film frames and video
frames, so that cadence may be maintained in mixed format environments.
The 10FID signal will be HIGH (default polarity) for one line at the start of the
10-field sequence. It will be LOW for all other lines. The signal’s rising and
falling edges will be simultaneous with the leading edge of the H Sync output
signal.
Alternatively, by setting bit 4 of the Video_Control register (see Section 3.10.3
on page 66), the 10FID output signal may be configured to go HIGH (default
polarity) on the leading edge of the H Sync output on line 1 of the first field in
the 10 field sequence, and be reset LOW on the leading edge of the H Sync
pulse of the first line of the second field in the 10 field sequence.
When in Genlock mode, the output 10FID signal will be phase locked to the
10FID reference input. If a 10FID input is not provided to the device, the user
must configure the 10FID output using register 1Ah of the host interface (see
Section 3.8.1 on page 57).
For applications involving audio, this signal may be used in place of the AFS
signal if the format selected is appropriate for a 10 field AFS repetition rate, and
the desired phase relationship of audio to video clock phasing coincides with
the desired film frame cadence.
The default polarity of this signal may be inverted by programming the Polarity
register at address 56h of the host interface (see Section 3.10.3 on page 66).
Please see Section 3.8.1 on page 57 for more detail on the 10FID output signal.
The Display Enable (DE) signal is used to indicate the display enable for
graphic display interfaces.
This signal will be HIGH (default polarity) whenever pixel information is to be
displayed on the display device (i.e. whenever both H Blanking and V Blanking
are in the active video state)
The width and timing of this signal will be determined by the timing parameters
of the selected video standard (see Table 1-2).
The default polarity of this signal may be inverted by programming the Polarity
register at address 56h of the host interface (see Section 3.10.3 on page 66).
TIMING_OUT_8
The Audio Frame Sync (AFS) signal is HIGH (default polarity) for the duration of –
the first line of the n’th video frame to indicate that the ACLK dividers are reset
at the start of line 1 of that frame. It is defined according to the frame rate of the
video format and the selected audio sample rate programmed via the
VID_STD[5:0] and ASR_SEL[2:0] pins or the host interface.
For example, if the video format is based on a 59.94Hz frame rate and the
audio sample rate clock is 48kHz, then n=5, and the AFS signal will be identical
to the 10FID signal.
By default, the AFS signal is reset by the 10 Field Identification (10FID)
reference input. This feature may be disabled using the Audio_Control register
at address 31h of the host interface (see Section 3.10.3 on page 66). The AFS
signal may also be reset using register 1Ah of the host interface. With no
reference, the frame divide by “n” controlling the AFS signal will free-run at an
arbitrary phase.
The default polarity of this signal may be inverted by programming the Polarity
register at address 56h of the host interface (see Section 3.10.3).
Please see Section 3.8.2 on page 58 for more detail on the AFS output signal.
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