GS4901B Datasheet, PDF(82/95 Page) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

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GS4901B Datasheet, PDF (82/95 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

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GS4901B/GS4900B Preliminary Data Sheet

Table 3-13: Configuration and Status Registers (Continued)

Address Bit

Description

R/W Default

V_Start_2

V_Stop_2

Operator_Polarity_2

5Eh

Reserved. Set this bit to zero when writing to 5Eh.

5Eh

14-0

The value programmed in this register indicates the start R/W

line number of the leading edge of the

user-programmed V Sync signal USER2_V. For

interlaced output standards, this value corresponds to

the odd field line number.

NOTE: The value programmed in this register must be

less than the value programmed in V_Stop_2.

Reference: Section 3.8.3 on page 59

5Fh

Reserved. Set this bit to zero when writing to 5Fh.

5Fh

14-0

The value programmed in this register indicates the end R/W

line number of the trailing edge of the user-programmed

V Sync signal USER2_V. For interlaced output

standards, this value corresponds to the odd field line

number.

NOTE: The value programmed in this register must not

exceed the maximum number of lines per field of the

outgoing standard.

Reference: Section 3.8.3 on page 59

60h

15-4

Reserved. Set these bits to zero when writing to 60h. â

60h

Polarity_2 - Use this bit to invert the polarity of the final R/W

USER2 signal.

By default, the polarity of the user programmed signals

is active LOW. The polarity may be switched to active

HIGH by setting this bit LOW.

Reference: Section 3.8.3 on page 59

60h

AND_2 - logical operator: USER2_H AND USER2_V R/W

Set this bit HIGH to output a signal that is only active

when both USER2_H and USER2_V are active.

When this bit is HIGH, bit 1 and bit 0 of this register will

be ignored.

Reference: Section 3.8.3 on page 59

60h

OR_2 - logical operator: USER2_H OR USER2_V

R/W

Set this bit HIGH to output a signal that is active

whenever USER2_H or USER2_V are active.

When this bit is HIGH bit 0 of this register will be

ignored.

Reference: Section 3.8.3 on page 59

60h

XOR_2 - logical operator: USER2_H XOR USER2_V R/W

Set this bit HIGH to output a signal with the following

attributes: Signal becomes active when either

USER2_H or USER2_V is active. Signal is inactive

when USER2_H and USER2_V are both active or both

inactive.

Reference: Section 3.8.3 on page 59

37703 - 0 April 2006

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