GS4901B Datasheet, PDF (47/95 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

GS4901B/GS4900B Preliminary Data Sheet
If the device determines that the output can be automatically genlocked to the input
reference, it will lock the output format to the reference, adjust the output timing
signals based on the genlock timing offset registers (Section 3.2.1.1 on page 37),
and then set the LOCK_LOST pin LOW.
If the device cannot automatically genlock the output to the applied reference, the
LOCK_LOST pin will be set HIGH and the device will operate in Free Run mode.
Individual H, V, and F-locked signals can be read from the Genlock_Status register
of the host interface. Additionally, designated bits in the Genlock_Control register
may be configured to permit the genlock block to ignore invalid timing on the
HSYNC, VSYNC, or FSYNC pin when determining the locked status of the device.
These registers are described in Section 3.9.3 on page 66.
The user may disable one or more of the 36 video standards listed in Table 1-2
from being used to genlock the output by setting the Reference_Standard_Disable
register located at address 11h-13h of the host interface. If a reference is applied
that is disabled in the Reference_Standard_Disable register, the lock process will
fail when the application layer sets GENLOCKb = LOW.
NOTE: If the device is already genlocked to an input reference and the applied
standard is subsequently disabled in the Reference_Standard_Disable register,
the device will remain locked.
By default, the HD video reference formats are disabled in the
Reference_Standard_Disable register and so must be enabled by the user before
attempting to lock to an HD reference. See Section 1.4 on page 20.
Table 3-4: Cross-reference Genlock Table
Input Reference Format
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 25 26 27 29 30 31 32 33 34 35 36 37 38
1
3
4
5
6
7
8
9
10
3.6.1 Adjustable Locking Time
The GS4901B/GS4900B offers two different locking mechanisms to allow the user
to control the PLL lock time and the integrity of the output signal during the locking
process. The locking process is said to take place after the application of the input
reference and before the LOCK_LOST signal is set LOW.
By default, the internal PLL will crash lock. This locking process will ensure a
minimum PLL locking time; however, crash lock will cause the phase of the output
clock and timing signals to jump during the locking process. The crash behaviour
of the video PLL is controlled by the Crash_Time bits of register address 24h.
Alternatively, the user may set bit 1 of register 16h HIGH to force the PLL to drift
lock. Drift lock will increase the locking time of the PLL, but will maintain the signal
integrity of the output clock and timing pulses during the locking process.
37703 - 0 April 2006
47 of 95