GS4901B Datasheet, PDF (68/95 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

GS4901B/GS4900B Preliminary Data Sheet
Table 3-13: Configuration and Status Registers (Continued)
Register Name
Address Bit
Description
R/W Default
Genlock_Status
15h
15-6
Reserved.
–
–
15h
5
Reference_Lock - this bit will be HIGH when the output R
N/A
is successfully genlocked to the input (i.e. when bits 4-1
of this register are HIGH and are not masked by bits 4-2
of register 16h).
The LOCK_LOST output pin is an inverted copy of this
bit.
Reference: Section 3.6.1 on page 47
15h
4
F_Lock - this bit will be HIGH when the output F is
R
N/A
successfully genlocked to the FSYNC input.
NOTE: If the input reference does not include an
FSYNC input, this bit will have the same setting as
V_Lock (bit 3).
Reference: Section 3.6.1 on page 47
15h
3
V_Lock - this bit will be HIGH when the output V is
R
N/A
successfully genlocked to the VSYNC input.
Reference: Section 3.6.1 on page 47
15h
2
H_Lock - this bit will be HIGH when the output H is
R
N/A
successfully genlocked to the HSYNC input.
Reference: Section 3.6.1 on page 47
15h
1
Clock_Lock - this bit will be HIGH when the video clock R
N/A
is locked to the internal V_pll AND the audio clock is
locked to the internal A_pll (i.e. bits 0 and 1 of register
1Fh are HIGH).
Reference: Section 3.6.1 on page 47
15h
0
Reference_Present - this bit will be HIGH when a valid R
N/A
input reference signal has been applied to the device.
The REF_LOST output pin is an inverted copy of this
bit.
Reference: Section 3.5.2 on page 43
37703 - 0 April 2006
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