GS4901B Datasheet, PDF (40/95 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

GS4901B/GS4900B Preliminary Data Sheet
3.4 Input Reference Signals
The HSYNC, VSYNC, FSYNC, and 10FID reference signals are applied to the
GS4901B/GS4900B via the designated input pins.
To operate in Genlock mode, the input reference signals must be valid and must
conform to a recognized video standard (see Section 3.5 on page 42).
In Free Run mode, no input reference is required.
Section 3.4.1 on page 40 describes the HSYNC, VSYNC and FSYNC input timing.
The 10FID input signal is discussed in Section 3.4.2 on page 41.
3.4.1 HSYNC, VSYNC, and FSYNC
The HSYNC, VSYNC, and FSYNC input reference signals may have analog
timing, such as from Gennum’s GS4981/82 sync separators (Figure 3-3), or may
have digital timing, such as from Gennum’s GS1559/60A/61 deserializers
(Figure 3-4). Section 1.4 on page 20 lists the 36 pre-programmed video timing
formats recognized by the GS4901B/GS4900B.
If the input reference format does not include an F sync signal, the FSYNC pin
should be held LOW.
HSYNC
VSYNC
FSYNC
Figure 3-3: Example HSYNC, VSYNC, and FSYNC Analog Input Timing from a
Sync Separator
PCLK
LUMA DATA OUT
CHROMA DATA OUT
H
V
F
3FF
3FF
000
000
H Signal Timing
Typical H Timing
Alternative H Timing
000
000
XYZ (eav)
XYZ (eav)
3FF
3FF
H:V:F TIMING - HD 20-BIT OUTPUT MODE
000
000
000
000
XYZ (sav)
XYZ (sav)
Figure 3-4: Example H Blanking, V Blanking, and F Digital Input Timing from an
SDI Deserializer
37703 - 0 April 2006
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