GS4901B Datasheet, PDF(73/95 Page) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

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GS4901B Datasheet, PDF (73/95 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

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GS4901B/GS4900B Preliminary Data Sheet

Table 3-13: Configuration and Status Registers (Continued)

Address Bit

Description

R/W Default

PCLK1_Phase/Divide

PCLK2_Phase/Divide

2Ch

15-7

Reserved. Set these bits to zero when writing to 2Ch. â

2Ch

Current_P1 - selects the current drive capability of the R/W

PCLK1 pin. Set this bit HIGH for high current drive.

Otherwise, the current drive will be low.

Reference: Section 3.7.1 on page 52

2Ch

5-2

PCLK1_Phase - adjusts the output phase of the PCLK1 R/W

clock with respect to the timing output pins. Phase is

delayed in 700ps (nominal) increments as shown in

Table 3-6.

Reference: Section 3.7.1 on page 52

2Ch

Divide_By_4 - set this bit HIGH to divide the output

R/W

PCLK1 by four.

NOTE: Setting this bit and bit 0 simultaneously HIGH

will hold the PCLK1 pin LOW.

Reference: Section 3.7.1 on page 52

2Ch

Divide_By_2 - set this bit HIGH to divide the output

R/W

PCLK1 by two.

NOTE: Setting this bit and bit 1 simultaneously HIGH

will hold the PCLK1 pin LOW.

Reference: Section 3.7.1 on page 52

2Dh

15-7

Reserved. Set these bits to zero when writing to 2Dh. â

2Dh

Current_P2 - selects the current drive capability of the R/W

PCLK2 pin. Set this bit HIGH for high current drive.

Otherwise, the current drive will be low.

Reference: Section 3.7.1 on page 52

2Dh

5-2

PCLK2_Phase - adjusts the output phase of the PCLK2 R/W

clock with respect to the timing output pins. Phase is

delayed in 700ps (nominal) increments as shown in

Table 3-6.

Reference: Section 3.7.1 on page 52

2Dh

Divide_By_4 - set this bit HIGH to divide the output

R/W

PCLK2 by four.

NOTE: Setting this bit and bit 0 simultaneously HIGH

will hold the PCLK2 pin LOW.

Reference: Section 3.7.1 on page 52

2Dh

Divide_By_2 - set this bit HIGH to divide the output

R/W

PCLK2 by two.

NOTE: Setting this bit and bit 1 simultaneously HIGH

will hold the PCLK2 pin LOW.

Reference: Section 3.7.1 on page 52

37703 - 0 April 2006

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