GS4901B Datasheet, PDF (48/95 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

GS4901B/GS4900B Preliminary Data Sheet
As discussed in Section 3.5.3 on page 44, the device will normally drift lock when
the reference is removed and subsequently re-applied during Genlock mode.
3.6.2 Adjustable Loop Bandwidth
The default loop bandwidth of the GS4901B/GS4900B's internal video PLL is 10Hz
when the output video standard is the same as the input reference format. For
other cross-locking combinations, the default loop bandwidth may be smaller than
1Hz or as large as 30Hz.
The user may adjust the loop bandwidth of both the video and audio PLLs
depending on the input, output, and audio standards selected. Increasing the loop
bandwidth will result in a shorter PLL lock time, but will allow more frequency
components of jitter to be passed to the outputs. Decreasing the loop bandwidth
will decrease the output jitter, but will result in a longer PLL lock time.
3.6.2.1 Loop Bandwidth of the Video PLL
The capacitive component of the filter controlling the video loop bandwidth is
determined by the Video_Cap_Genlock register and the resistive component is
determined by the Video_Res_Genlock register. These two registers are located
at addresses 26h and 27h, respectively, of the host interface.
To determine the setting of Video_Res_Genlock and Video_Cap_Genlock, the
following equations must be solved:
Video_Res_Genlock = 47 + log₂(6 × BW × JITTERIN × H_Feedback_Divide )
Video_Cap_Genlock ≤ Video_Res_Genlock – 21
where:
BW = the desired video PLL loop bandwidth
JITTERIN = Jitter present on applied HSYNC reference signal, in seconds
H_Feedback_Divide = the numerator of the video PLL divide ratio
H_Feedback_Divide represents the numerator of the ratio of the output clock
frequency to the frequency of the H reference signal.
37703 - 0 April 2006
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