GS4901B Datasheet, PDF(80/95 Page) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

GS4901B Datasheet, PDF (80/95 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

◁

GS4901B/GS4900B Preliminary Data Sheet

Table 3-13: Configuration and Status Registers (Continued)

Address Bit

Description

R/W Default

H_Start_1

H_Stop_1

V_Start_1

56h

F_Sync - set this bit HIGH to invert the polarity of the F R/W

Sync timing output signal.

By default, the F Sync signal will be HIGH for the entire

period of field 1.

Reference: Table 1-3

56h

V_Blanking - set this bit HIGH to invert the polarity of the R/W

V Blanking timing output signal.

By default, the V Blanking signal will be LOW for the

portion of the field/frame containing valid video data.

Reference: Table 1-3

56h

V_Sync - set this bit HIGH to invert the polarity of the V R/W

Sync timing output signal.

By default, the V Sync signal is active LOW.

Reference: Table 1-3

56h

H_Blanking - set this bit HIGH to invert the polarity of R/W

the H Blanking timing output signal.

By default, the H Blanking signal will be LOW for the

portion of the video line containing valid video samples.

Reference: Table 1-3

56h

H_Sync - set this bit HIGH to invert the polarity of the H R/W

Sync timing output signal.

By default, the H Sync signal is active LOW.

Reference: Table 1-3

57h

15-0

The value programmed in this register indicates the

R/W

pixel start point for the leading edge of the

user-programmed H Sync signal USER1_H.

NOTE: The value programmed in this register must be

less than the value programmed in H_Stop_1.

Reference: Section 3.8.3 on page 59

58h

15-0

The value programmed in this register indicates the

R/W

pixel end point for the trailing edge of the

user-programmed H Sync signal USER1_H.

NOTE: The value programmed in this register must not

exceed the maximum number of clock periods per line

of the outgoing standard.

Reference: Section 3.8.3 on page 59

59h

Reserved. Set this bit to zero when writing to 59h.

59h

14-0

The value programmed in this register indicates the start R/W

line number of the leading edge of the

user-programmed V Sync signal USER1_V. For

interlaced output standards, this value corresponds to

the odd field number.

NOTE: The value programmed in this register must be

less than the value programmed in V_Stop_1.

Reference: Section 3.8.3 on page 59

37703 - 0 April 2006

80 of 95

▷