GS4901B Datasheet, PDF (16/95 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

GS4901B/GS4900B Preliminary Data Sheet
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
46, 47
PCLK3, PCLK3
–
48
LVDS/PCLK3_GND –
49
PCLK2
–
Type Description
Output
Power
Supply
Output
CLOCK SIGNAL OUTPUTS
Signal levels are LVDS compatible.
Differential video clock output signal.
PCLK3/PCLK3 present a differential video sample rate clock output to
the application layer.
By default, after system reset, this output will operate at the fundamental
frequency determined by the setting of the VID_STD[5:0] pins. It is
possible to define other non-standard fundamental clock rates using the
host interface.
It is also possible to select different division ratios for the
PCLK3/PCLK3 outputs by programming designated registers in the
host interface. A clock output of the fundamental rate, fundamental rate
÷2, or fundamental rate ÷4 may be selected.
The PCLK3/PCLK3 outputs will be high impedance when
VID_STD[5:0] = 00h.
Ground connection for PCLK3 output circuitry and LVDS driver. Connect
to GND.
CLOCK SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Video clock output signal.
PCLK2 presents a video sample rate clock output to the application
layer.
By default, after system reset, the PCLK2 output pin will operate at the
fundamental frequency determined by the setting of the VID_STD[5:0]
pins. It is possible to define other non-standard fundamental clock rates
using the host interface.
It is also possible to select different division ratios for the PCLK2 output
by programming designated registers in the host interface. A clock
output of the fundamental rate, fundamental rate ÷2, or fundamental rate
÷4 may be selected.
By setting designated registers in the host interface, the current drive
capability of this pin may be set high or low. By default, the current drive
will be low.
The PCLK2 output will be held LOW when VID_STD[5:0] = 00h.
37703 - 0 April 2006
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