GS4901B Datasheet, PDF(65/95 Page) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

GS4901B Datasheet, PDF (65/95 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

◁

GS4901B/GS4900B Preliminary Data Sheet

Table 3-12: GSPI Timing Parameters

Parameter Definition

The minimum duration of time chip select, CS, must be

LOW before the first SCLK rising edge.

The minimum SCLK period.

Duty cycle tolerated by SCLK.

Minimum input setup time.

The minimum duration of time between the last SCLK

command word (or data word if the Auto-Increment bit is

HIGH) and the first SCLK of the data word (write cycle).

The minimum duration of time between the last SCLK

command word (or data word if the Auto-Increment bit is

HIGH) and the first SCLK of the data word (read cycle).

Minimum output hold time (15pF load).

The minimum duration of time between the last SCLK of

the GSPI transaction and when CS can be set HIGH.

Minimum input hold time.

Specification

1.5 ns

100 ns

40% to 60%

1.5 ns

37.1 ns

148.4 ns

1.5 ns

37.1 ns

1.5 ns

SCLK

SDIN

R/W

RSV RSV AutoInc A11 A10 A9

SDOUT

R/W RSV RSV AutoInc A11 A10

D15 D14 D13 D12 D11 D10 D9

Figure 3-14: GSPI Read Mode Timing

SCLK

SDIN R/W RSV RSV AutoInc A11 A10

A4 A3

SDOUT R/W RSV RSV AutoInc A11

A10

D15 D14 D13 D12 D11 D10 D9

Figure 3-15: GSPI Write Mode Timing

37703 - 0 April 2006

65 of 95

▷