GS4901B Datasheet, PDF (74/95 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

GS4901B/GS4900B Preliminary Data Sheet
Table 3-13: Configuration and Status Registers (Continued)
Register Name
Address Bit
Description
R/W Default
PCLK3_Phase/Divide
PCLK3_Tristate
RSVD
2Eh
15-6
Reserved. Set these bits to zero when writing to 2Eh. –
–
2Eh
5-2
PCLK3_Phase - adjusts the output phase of the
R/W
0
PCLK3/PCLK3 clock with respect to the timing output
pins. Phase is delayed in 700ps (nominal) increments
as shown in Table 3-6.
Reference: Section 3.7.1 on page 52
2Eh
1
Divide_By_4 - set this bit HIGH to divide the output
R/W
0
PCLK3/PCLK3 by four.
Setting this bit and bit 0 simultaneously HIGH will give
the full rate video clock on the PCLK3 / PCLK3 pins.
Reference: Section 3.7.1 on page 52
2Eh
0
Divide_By_2 - set this bit HIGH to divide the output
R/W
0
PCLK3/PCLK3 by two.
Setting this bit and bit 1 simultaneously HIGH will give
the full rate video clock on the PCLK3 / PCLK3 pins.
Reference: Section 3.7.1 on page 52
2Fh
15-2
Reserved. Set these bits to zero when writing to 2Fh. –
–
2Fh
1-0
Set these bits to 11b to tristate the PCLK3 / PCLK3 pins. R/W
00b
Reference: Section 3.7.1 on page 52
2Fh - 30h –
Reserved.
–
–
37703 - 0 April 2006
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