GS4901B Datasheet, PDF(69/95 Page) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

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GS4901B Datasheet, PDF (69/95 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

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GS4901B/GS4900B Preliminary Data Sheet

Table 3-13: Configuration and Status Registers (Continued)

Address Bit

Description

R/W Default

Genlock_Control

RSVD

16h

17h-19h

15-7

Reserved. Set these bits to zero when writing to 16h. â

This bit is used to enable the Extended Audio Mode of R/W

the device.

Genlock_From_Host - set this bit HIGH to enable video R/W

genlock control via the Host Interface instead of the

external GENLOCK pin (see bit 0 of this register).

Reference: Section 3.2 on page 34

F_Lock_Mask - if this bit is set HIGH, the

R/W

GS4901B/GS4900B will ignore the status of F_Lock (bit

4 of register 15h) when determining the status of

Reference_Lock (bit 5 of register 15h).

Reference: Section 3.6.1 on page 47

V_Lock_Mask - if this bit is set HIGH, the

R/W

GS4901B/GS4900B will ignore the status of V_Lock (bit

3 of register 15h) when determining the status of

Reference_Lock (bit 5 of register 15h).

Reference: Section 3.6.1 on page 47

H_Lock_Mask - if this bit is set HIGH, the

R/W

GS4901B/GS4900B will ignore the status of H_Lock (bit

2 of register 15h) when determining the status of

Reference_Lock (bit 5 of register 15h).

Reference: Section 3.6.1 on page 47

Drift_Crash - when this bit is set HIGH, the generated R/W

video clock will drift lock to a new input reference rather

than crash lock.

Reference: Section 3.6.1 on page 47

GENLOCK - this bit may be used instead of the external R/W

pin to Genlock the output video format to the input

reference. This bit will be ignored if bit 5 of this register

is LOW.

Reference: Section 3.2 on page 34

Reserved

37703 - 0 April 2006

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