GS4901B Datasheet, PDF (79/95 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

GS4901B/GS4900B Preliminary Data Sheet
Table 3-13: Configuration and Status Registers (Continued)
Register Name
Address Bit
Description
R/W Default
RSVD
Video_Control
VID_STD[5:0]
RSVD
Polarity
4Bh
4Ch
4Ch
4Ch
4Ch
4Ch
4Dh
4Dh
4Eh-55h
56h
56h
56h
56h
56h
56h
–
Reserved.
–
–
15-5
Reserved. Set these bits to zero when writing to 4Ch. –
–
4
10FID_F_pulse - set this bit HIGH to stretch the 10FID R/W
0
pulse duration from 1 line to 1 field.
Reference: Section 3.8.1 on page 57
3-2
Reserved. Set these bits to zero when writing to 4Ch. –
–
1
Host_VID_STD - set this bit HIGH to select the output R/W
0
video standard using register 4Dh instead of the
external VID_STD[5:0] pins.
The external VID_STD[5:0] pins will be ignored, but
should not be left floating.
Reference: Section 1.4 on page 20
0
Reserved. Set this bit to zero when writing to 4Ch.
–
–
15-6
Reserved. Set these bits to zero when writing to 4Dh. –
–
5-0
Replaces the external VID_STD[5:0] pins when
VID_From_Host (bit 1 of address 4Ch) is HIGH.
Reference: Section 1.4 on page 20
R/W
00h
–
Reserved
–
–
15-10 Reserved. Set these bits to zero when writing to 56h. –
–
9
AFS (GS4901B only)- set this bit HIGH to invert the
R/W
0
polarity of the AFS timing output signal.
By default, the AFS signal is HIGH for the duration of
the first line of the n’th video frame to indicate that the
ACLK dividers have been reset at the start of line 1 of
that frame.
NOTE: The GS4900B does not generate an AFS pulse
and will ignore the setting of this bit.
Reference: Table 1-3
8
10FID - set this bit HIGH to invert the polarity of the
R/W
0
10FID timing output signal.
By default, the 10FID signal will go HIGH for one line at
the start of the 10-field sequence.
Reference: Table 1-3
7
DE - set this bit HIGH to invert the polarity of the DE
R/W
0
timing output signal.
By default, the DE signal will be HIGH whenever pixel
information is to be displayed on the display device
Reference: Table 1-3
6
Reserved. Set this bit to zero when writing to 56h.
–
–
5
F_Digital - set this bit HIGH to invert the polarity of the F R/W
0
Digital timing output signal.
By default, the F Digital signal will be HIGH for the entire
period of field 1.
Reference: Table 1-3
37703 - 0 April 2006
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