GS4901B Datasheet, PDF (84/95 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

GS4901B/GS4900B Preliminary Data Sheet
Table 3-13: Configuration and Status Registers (Continued)
Register Name
Address Bit
Description
R/W Default
Operator_Polarity_3
H_Start_4
H_Stop_4
V_Start_4
65h
15-4
Reserved. Set these bits to zero when writing to 65h. –
–
65h
3
Polarity_3 - Use this bit to invert the polarity of the final R/W
1
USER3 signal.
By default, the polarity of the user programmed signals
is active LOW. The polarity may be switched to active
HIGH by setting this bit LOW.
Reference: Section 3.8.3 on page 59
65h
2
AND_3 - logical operator: USER3_H AND USER3_V R/W
0
Set this bit HIGH to output a signal that is only active
when both USER3_H and USER3_V are active.
When this bit is HIGH, bit 1 and bit 0 of this register will
be ignored.
Reference: Section 3.8.3 on page 59
65h
1
OR_3 - logical operator: USER3_H OR USER3_V
R/W
0
Set this bit HIGH to output a signal that is active
whenever USER3_H or USER3_V are active.
When this bit is HIGH bit 0 of this register will be
ignored.
Reference: Section 3.8.3 on page 59
65h
0
XOR_3 - logical operator: USER3_H XOR USER3_V R/W
0
Set this bit HIGH to output a signal with the following
attributes: Signal becomes active when either
USER3_H or USER3_V is active. Signal is inactive
when USER3_H and USER3_V are both active or both
inactive.
Reference: Section 3.8.3 on page 59
66h
15-0
The value programmed in this register indicates the
R/W
0
pixel start point for the leading edge of the
user-programmed H Sync signal USER4_H.
NOTE: The value programmed in this register must be
less than the value programmed in H_Stop_4.
Reference: Section 3.8.3
67h
15-0
The value programmed in this register indicates the
R/W
0
pixel end point for the trailing edge of the
user-programmed H Sync signal USER4_H.
NOTE: The value programmed in this register must not
exceed the maximum number of clock periods per line
of the outgoing standard.
Reference: Section 3.8.3 on page 59
68h
15
Reserved. Set this bit to zero when writing to 68h.
–
–
68h
14-0
The value programmed in this register indicates the start R/W
0
line number of the leading edge of the
user-programmed V Sync signal USER4_V. For
interlaced output standards, this value corresponds to
the odd field line number.
NOTE: The value programmed in this register must be
less than the value programmed in V_Stop_4.
Reference: Section 3.8.3 on page 59
37703 - 0 April 2006
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