GS4901B Datasheet, PDF (11/95 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

GS4901B/GS4900B Preliminary Data Sheet
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
12
ANALOG_GND
–
Power
Supply
13
AUD_PLL_GND
–
(GS4901B only)
Power
Supply
ANALOG_GND
–
(GS4900B only)
Power
Supply
14
AUD_PLL_VDD
–
(GS4901B only)
Power
Supply
ANALOG_GND
–
(GS4900B only)
Power
Supply
15
10FID
Non
Input
Synchronous
16
HSYNC
Non
Input
Synchronous
17
VSYNC
Non
Input
Synchronous
18, 31, 38, IO_VDD
–
Power
50, 62
Supply
Description
Ground connection for the analog input block. Connect to GND.
Ground connection for the audio clock synthesis internal block. Connect
to GND.
Ground connection for the analog input block. Connect to GND.
Most positive power supply connection for the audio clock synthesis
internal block. Connect to +1.8V DC.
Ground connection for the analog input block. Connect to GND.
REFERENCE SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
The 10FID external reference signal is applied to this pin by the
application layer. 10FID defines the field in which the video and audio
clock phase relationship is defined according to SMPTE 318-M. It is also
used to define a 3:2 video cadence.
NOTE: If the input reference format does not include a 10 Field ID signal,
this pin should be held LOW. See Section 3.4.2 on page 41.
REFERENCE SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
The HSYNC external reference signal is applied to this pin by the
application layer. When the GS4901B/GS4900B is operating in Genlock
mode, the device senses the polarity of the HSYNC input automatically,
and references to the leading edge.
This signal must adhere to one of the 36 defined video standards
supported by the device. In this mode of operation, the HSYNC input
provides a horizontal scanning reference signal.
The HSYNC signal may have analog timing, such as from a sync
separator, or may be digital such as from an SDI deserializer. Section 1.4
on page 20 describes the 36 video formats recognized by the
GS4901B/GS4900B.
REFERENCE SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
The VSYNC external reference signal is applied to this pin by the
application layer. When the GS4901B/GS4900B is operating in Genlock
mode, the device senses the polarity of the VSYNC input automatically,
and references to the leading edge.
This signal must adhere to one of the 36 defined video standards
supported by the device. In this mode of operation, the VSYNC input
provides a vertical scanning reference signal.
The VSYNC signal may have analog timing, such as from a sync
separator, or may be digital such as from an SDI deserializer. Section 1.4
on page 20 describes the 36 video formats recognized by the
GS4901B/GS4900B.
Most positive power supply connection for the digital I/O signals.
Connect to either +1.8V DC or +3.3V DC.
NOTE: All five IO_VDD pins must be powered by the same voltage.
37703 - 0 April 2006
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