GS4901B Datasheet, PDF (55/95 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

GS4901B/GS4900B Preliminary Data Sheet
The fs signal on ACLK1-3 has an accurate 50% duty cycle, and can be used for
left/right definition, with the following exception: if fs = 96kHz and the user
configures the host interface such that one of the three ACLK pins is set to output
a clock signal at 192fs or 384fs, the 512fs clock will have a 33% duty cycle.
All audio clocks are initially reset on the rising edge of the AFS pulse, ensuring that
video to audio clock synchronization is correct. During normal operation, the audio
clock edge is allowed to drift slightly with respect to the AFS pulse. By default, the
audio clock will be reset directly by the AFS pulse if it drifts more than
approximately +/-0.1us from the rising edge of the AFS pulse. However, after
device reset, or after the application of a new input reference, the ACLK outputs
may sometimes be offset from the AFS pulse by up to several microseconds. The
offset will remain until the device is reset or the reference removed and re-applied.
The user may avoid this offset by minimizing the width of the AFS_Reset_Window
using bits 9-7 of register 31h for the duration of the audio PLL locking process.
Once the audio PLL is locked, bit 1 of register 1Fh will be set HIGH, and the
AFS_Reset_Window may be set as desired. See Table 3-9.
Table 3-9: Encoding Scheme for AFS_Reset_Window
Window Tolerance (us)
AFS_Reset_Window
(address 31h)
fs = 32kHz
fs = 44.1kHz
000
0.044
0.033
001
0.084
0.062
010
(default)
0.166
0.121
011
0.329
0.239
1XX
0.654
0.475
NOTE: ‘X’ signifies ‘don’t care.’ The bit setting will be ignored.
fs = 48 kHz
0.030
0.057
0.112
0.220
0.437
fs = 96 kHz
(enable_384fs = 1)
0.030
0.057
0.112
fs = 96 kHz
(enable_384fs = 0)
0.044
0.084
0.166
0.220
0.437
0.329
0.654
3.7.2.1 Audio to Video Clock Phasing
The important aspect of the audio to video phase relates to the way in which the
AFS pulse is used to reset the audio clock dividers so as to line up the leading edge
of the audio clocks with the leading edge of the H Sync pulse on line 1 of the first
field in the audio frame sequence. The AFS pulse is further discussed in
Section 3.8.2 on page 58.
625i 50 Format
For the 48kHz sampling rate, the audio to video phase relationship for 625/50i
reference signals is provided by the device in accordance with the EBU
recommended practice R83-1996. The start of an audio frame (fs clock) will align
with the 50% point of the H sync input of line 1 of each video frame (+/- the
allowable drift specified in Table 3-9).
37703 - 0 April 2006
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