MB81F643242C Datasheet, PDF (5/56 Pages) Fujitsu Component Limited. – 4 X 512 K X 32 BIT SYNCHRONOUS DYNAMIC RAM

MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
s BLOCK DIAGRAM
Fig. 1 – MB81F643242C BLOCK DIAGRAM
CLK
To each block
CLOCK
BUFFER
CKE
CS
RAS
COMMAND
DECODER
CAS
WE
A0 to A9,
A10/AP
BA1
BA0
ADDRESS
BUFFER/
REGISTER
CONTROL
SIGNAL
LATCH
MODE
REGISTER
RAS
BANK-3
BANK-2
BANK-1
BANK-0
CAS
WE
DRAM
CORE
(2,048 × 256 × 32)
ROW
ADDR.
DQM0
to
DQM3
DQ0
to
DQ31
I/O DATA
BUFFER/
REGISTER
COLUMN
ADDRESS
COUNTER
COL.
ADDR.
I/O
VCC
VCCQ
VSS
VSSQ
5