MB81F643242C Datasheet, PDF (37/56 Pages) Fujitsu Component Limited. – 4 X 512 K X 32 BIT SYNCHRONOUS DYNAMIC RAM

MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
TIMING DIAGRAM – 5 : DQM0 - DQM3 - INPUT MASK AND OUTPUT DISABLE (@ BL = 4)
CLK
DQM0 to DQM3
(@ Read)
DQ0 to DQ31
(@ Read)
DQM0 to DQM3
(@ Write)
DQ0 to DQ31
(@ Write)
IDQZ (2 clocks)
Q1
Q2
Hi-Z
Q4
End of burst
IDQD (same clock)
D1
MASKED
D3
D4
End of burst
TIMING DIAGRAM – 6 : PRECHARGE TIMING (APPLIED TO THE SAME BANK)
CLK
Command
ACTV
Note: PRECHARGE means ’ PRE’ or ’PALL’.
tRAS (min)
PRE
37