MB81F643242C Datasheet, PDF (46/56 Pages) Fujitsu Component Limited. – 4 X 512 K X 32 BIT SYNCHRONOUS DYNAMIC RAM

MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
SCITT TEST SEQUENCE
The followings are the SCITT test sequence. SCITT Test can be executed after power-on and prior to Precharge
command in POWER-UP INITIALIZATION. Once Precharge command is issued to SDRAM, it never get back to
SCITT Test Mode during regular operation for the purpose of a fail-safe way in get in and out of test mode.
1. Apply power. Attempt to maintain either NOP or DESL command at the input.
2. Maintain stable power for a minimum of 100us.
3. Enter SCITT test mode.
4. Execute SCITT test.
5. Exit from SCITT mode.
It is required to follow Power On Sequence to execute read or write operation.
6. Start clock. Attempt to maintain either NOP or DESL command at the input.
7. Precharge all banks by Precharge (PRE) or Precharge All command (PALL).
8. Assert minimum of 2 Auto-Refresh command (REF).
9. Program the mode register by Mode Register Set command (MRS).
The 3,4,5 steps define the SCITT mode available. It is possible to skip these steps if necessary (Refer to POWER-
UP INITIALIZATION).
COMMAND TRUTH TABLE Note *1
Control
Input
Output
CAS
CS
CKE
WE
RAS
A0 to A10
BA0, BA1
DQM0
to
DQM3
CLK
DQ0
to
DQ31
SCITT mode entry H→L *²
L
L
X
X
X
X
X
X
SCITT mode exit L→H *³ H ^*5
L ^*5
X
X
X
X
X
X
SCITT mode
output enable *⁴
L
L
H
V
V
V
V
V
V
Notes: *1.
*2.
*3.
*4.
*5.
L = Logic Low, H = Logic High, V = Valid, X = either L or H
The SCITT mode entry command assumes the first CAS falling edge with CS and CKE = L after power
on.
The SCITT mode exit command assumes the first CAS rising edge after the test mode entry.
Refer the test code table.
CS = H or CKE = L is necessary to disable outputs in SCITT mode exit.
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