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| MB81F643242C Datasheet, PDF (44/56 Pages) Fujitsu Component Limited. – 4 X 512 K X 32 BIT SYNCHRONOUS DYNAMIC RAM | |||
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MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
TIMING DIAGRAM â 17 : MODE REGISTER SET TIMING
CLK
Command
MRS
tRSC (min)
NOP or DESL
ACTV
Address
MODE
ROW
ADDRESS
Notes: The Mode Register Set command (MRS) should only be asserted after all banks have been precharged.
44
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