MB81F643242C Datasheet, PDF (30/56 Pages) Fujitsu Component Limited. – 4 X 512 K X 32 BIT SYNCHRONOUS DYNAMIC RAM

MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
BASE VALUES FOR CLOCK COUNT/LATENCY
Parameter Notes
MB81F643242C MB81F643242C MB81F643242C Reference Value ^*4
Symbol
-60
-70
-10
@67MHz, CL=3 _Unit
Min. Max. Min. Max. Min. Max. Min. Max.
RAS Cycle
Time
*9
tRC
60 — 63 — 90 — 110
—
ns
RAS Precharge Time
tRP
18 — 20 — 30 —
40
—
ns
RAS Active Time
tRAS
42 110K 42 110K 60 110K 70
110K ns
RAS to CAS Delay Time
tRCD
18
—
20
—
30
—
30
—
ns
Write Recovery Time
tWR
6
—
7
— 10 —
15
—
ns
RAS to RAS Bank Active
Delay Time
tRRD
12
—
14
—
20
—
30
—
ns
Data-in to Precharge Lead
Time
tDPL
7
—
7
— 10 —
15
—
ns
Data-in to Active/
CL=2
tDAL2
1 cyc
+ tRP
—
1 cyc
+ tRP
—
1 cyc
+ tRP
—
1 cyc
+ tRP
—
ns
Refresh Command
Period
CL=3
tDAL3
2 cyc
+ tRP
—
2 cyc
+ tRP
—
2 cyc
+ tRP
—
2 cyc
+ tRP
—
ns
Mode Resister Set Cycle
Time
tRSC
12
—
14
—
20
—
30
—
ns
CLOCK COUNT FORMULA Note *10
Clock ≥
Base Value
Clock Period
(Round off a whole number)
30