MB81F643242C Datasheet, PDF (48/56 Pages) Fujitsu Component Limited. – 4 X 512 K X 32 BIT SYNCHRONOUS DYNAMIC RAM

MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
AC SPECIFICATION
Parameter
tTS
tTH
tEPD
tTLZ
tTHZ
tTCA
tTIA
tTOH
tETD
tTIH
Description
Test mode entry set up time
Test mode entry hold time
Test mode exit to power on sequence delay time
Test mode output in Low-Z time
Test mode output in High-Z time
Test mode access time from control signals
(output enable & chip select)
Test mode Input access time
Test mode Output Hold time
Test mode entry to test delay time
Test mode input hold time
TIMING DIAGRAMS
Minimum
10
10
10
0
0
—
—
0
10
30
Maximum
—
—
—
—
20
40
20
—
—
—
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TIMING DIAGRAM – 1 : POWER-UP TIMING DIAGRAM
*2
VDD
100µs Pause Time
Test Mode Entry Point
CS
CKE
CAS
*3
*1
Notes: *1. SCITT is enabled if CS = L, CKE = L, CAS = L at just power on.
*2. All output buffers maintains in High-Z state regardless of the state of control signals as long as
the above timing is maintained.
*3. CAS must not be brought from High to Low.
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