MB81F643242C Datasheet, PDF (1/56 Pages) Fujitsu Component Limited. – 4 X 512 K X 32 BIT SYNCHRONOUS DYNAMIC RAM

FUJITSU SEMICONDUCTOR
DATA SHEET
ADVANCED INFO.
AE0.1E
MEMORY
CMOS
4 × 512 K × 32 BIT
SYNCHRONOUS DYNAMIC RAM
MB81F643242C-60/-70/-10
CMOS 4-Bank × 524,288-Word × 32 Bit
Synchronous Dynamic Random Access Memory
s DESCRIPTION
The Fujitsu MB81F643242C is a CMOS Synchronous Dynamic Random Access Memory (SDRAM) containing
67,108,864 memory cells accessible in a 32-bit format. The MB81F643242C features a fully synchronous
operation referenced to a positive edge clock whereby all operations are synchronized at a clock input which
enables high performance and simple user interface coexistence. The MB81F643242C SDRAM is designed to
reduce the complexity of using a standard dynamic RAM (DRAM) which requires many control signal timing
constraints, and may improve data bandwidth of memory as much as 5 times more than a conventional DRAM.
The MB81F643242C is ideally suited for workstations, personal computers, laser printers, high resolution graphic
adapters/accelerators and other applications where an extremely large memory and bandwidth are required and
where a simple interface is needed.
s PRODUCT LINE & FEATURES
Parameter
CL - tRCD - tRP
CL = 2
CL = 3
Clock Frequency
CL = 2
Burst Mode Cycle Time
CL = 3
CL = 2
Access Time from Clock
CL = 3
Operating Current
Power Down Mode Current (ICC2P)
Self Refresh Current (ICC6)
-60
2 - 2 - 2 clk min.
3 - 3 - 3 clk min.
167 MHz max.
10 ns min.
6 ns min.
6 ns max.
5.5 ns max.
165 mA max.
MB81F643242C
-70
-10
2 - 2 - 2 clk min. 2 - 2 - 2 clk min.
3 - 3 - 3 clk min. 3 - 3 - 3 clk min.
143 MHz max. 100 MHz max.
10 ns min.
15 ns min.
7 ns min.
10 ns min.
6 ns max.
7 ns max.
5.5 ns max.
7 ns max.
155 mA max.
115 mA max.
2 mA max.
2 mA max.
Reference
Value@ 67 MHz,
CL=3
2 - 2 - 2 clk min.
3 - 3 - 3 clk min.
67 MHz max.
20 ns min.
15 ns min.
7 ns max.
7 ns max.
100 mA max.
• Single +3.3 V Supply ±0.3 V tolerance
• LVTTL compatible I/O interface
• 4 K refresh cycles every 64 ms
• Four bank operation
• Burst read/write operation and burst
read/single write operation capability
• Programmable burst type, burst length, and
CAS latency
• Auto-and Self-refresh (every 15.6 µs)
• CKE power down mode
• Output Enable and Input Data Mask