MB81F643242C Datasheet, PDF (12/56 Pages) Fujitsu Component Limited. – 4 X 512 K X 32 BIT SYNCHRONOUS DYNAMIC RAM

MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
(Continued)
Current
State
Refreshing
CS RAS CAS WE
HXXX
L HHX
LHLX
L
L
H
X
Mode
Register
Setting
L
L
L
X
HXXX
L HHH
L HH L
LHLX
L
L
X
X
Addr
X
X
X
X
X
X
X
X
X
X
Command
Function
DESL
NOP (Idle after tRC)
NOP/BST NOP (Idle after tRC)
READ/READA/
WRIT/WRITA
Illegal
ACTV/
PRE/PALL
Illegal
REF/SELF/
MRS
Illegal
DESL
NOP (Idle after tRSC)
NOP
NOP (Idle after tRSC)
BST
Illegal
READ/READA/
WRIT/WRITA
Illegal
ACTV/PRE/
PALL/REF/
SELF/MRS
Illegal
Notes
ABBREVIATIONS:
RA = Row Address
CA = Column Address
BA = Bank Address
AP = Auto Precharge
Notes: *1.
*2.
*3.
*4.
*5.
*6.
*7.
All entries in OPERATION COMMAND TABLE assume the CKE was High during the proceeding clock
cycle and the current clock cycle.
Illegal means don’t used command. If used, power up sequence be asserted after power shut down.
Illegal to bank in specified state; entry may be legal in the bank specified by BA, depending on the state
of that bank.
Illegal if any bank is not idle.
Must satisfy bus contention, bus turn around, and/or write recovery requirements.
Refer to “TIMING DIAGRAM -11 & -12” in section “s TIMING DIAGRAMS“.
NOP to bank precharging or in idle state. May precharge bank specified by BA (and AP).
SELF command should only be issued after the last read data have been appeared on DQ.
MRS command should only be issued on condition that all DQ are in Hi-Z.
12