MB81F643242C Datasheet, PDF (34/56 Pages) Fujitsu Component Limited. – 4 X 512 K X 32 BIT SYNCHRONOUS DYNAMIC RAM

MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
Fig. 7 – TIMING DIAGRAM, PULSE WIDTH
CLK
Input
(Control)
COMMAND
tRC, tRP, tRAS, tRCD, tWR, tREF,
tDPL, tDAL, tRSC, tRRD, tCKSP
COMMAND
Note: These parameters are a limit value of the rising edge of the clock from one command input to next input. tCKSP is the
latency value from the rising edge of CKE.
Measurement reference voltage is 1.4 V.
Fig. 8 – TIMING DIAGRAM, ACCESS TIME
CLK
Command
DQ0 to DQ31
(Output)
READ
tAC
(CAS Latency – 1) × tCK
tAC
tAC
Q(Valid)
Q(Valid)
Q(Valid)
34