MB81F643242C Datasheet, PDF (42/56 Pages) Fujitsu Component Limited. – 4 X 512 K X 32 BIT SYNCHRONOUS DYNAMIC RAM

MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
TIMING DIAGRAM – 13 : READ WITH AUTO-PRECHARGE
(EXAMPLE @ CL = 2, BL = 2 Applied to same bank)
CLK
Command
ACTV
DQM
(DQM0 to DQM3)
tRAS (min)
READA
2 clocks ^*1
(same value as BL)
tRP (min)
NOP or DESL
BL+tRP (min) ^*2
DQ0 to DQ31
Q1
Q2
ACTV
Notes: *1. Precharge at read with Auto-precharge command (READA) is started from number of clocks that is the same as
Burst Length (BL) after the READA command is asserted.
*2. Next ACTV command should be issued after BL+tRP (min) from READA command.
TIMING DIAGRAM – 14 : WRITE WITH AUTO-PRECHARGE *1, *2, and *3
(EXAMPLE @ CL = 2, BL = 2 Applied to same bank)
tRAS (min)
CLK
Command
ACTV
WRITA
CL- 1 ^*4
tDAL (min)
BL+tRP (min) ^*5
NOP or DESL
ACTV
DQM
(DQM0 to DQM3)
DQ0 to DQ31
D1
D2
Notes: *1. Even if the final data is masked by DQM, the precharge does not start the clock of final data input.
*2. Once auto precharge command is asserted, no new command within the same bank can be issued.
*3. Auto-precharge command doesn’t affect at full column burst operation except Burst READ & Single Write.
*4. Precharge at write with Auto-precharge is started after the CL - 1 from the end of burst.
*5. Next command should be issued after BL+ tRP (min) at CL = 2, BL+1+tRP (min) at CL = 3 from WRITA command.
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