MB81F643242C Datasheet, PDF (31/56 Pages) Fujitsu Component Limited. – 4 X 512 K X 32 BIT SYNCHRONOUS DYNAMIC RAM

MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
LATENCY - FIXED VALUES
(The latency values on these parameters are fixed regardless of clock period.)
Parameter
CKE to Clock Disable
DQM to Output in High-Z
Symbol
MB81F643242C
-60
lCKE
1
lDQZ
2
MB81F643242C
-70
MB81F643242C
-10
Unit
1
1
cycle
2
2
cycle
DQM to Input Data Delay
lDQD
0
Last Output to Write Command Delay
lOWD
2
Write Command to Input Data Delay
lDWD
0
0
0
cycle
2
2
cycle
0
0
cycle
Precharge to Outputing
High-Z Delay
CL = 2 lROH2
2
CL = 3 lROH3
3
Burst Stop Command to Output
CL = 2 lBSH2
2
in High-Z Delay
CL = 3 lBSH3
3
CAS to CAS Delay (min)
lCCD
1
CAS Bank Delay (min)
lCBD
1
2
2
cycle
3
3
cycle
2
2
cycle
3
3
cycle
1
1
cycle
1
1
cycle
Notes: *1.
*2.
*3.
*4.
*5.
*6.
*7.
*8.
*9.
*10.
AC characteristics are measured after following the POWER-UP INITIALIZATION procedure in section
“s FUNCTIONAL DESCRIPTION“.
AC characteristics assume tT = 1 ns and 30 pF of capacitive load.
1.4 V is the reference level for measuring timing of input signals. Transition times are measured
between VIH (min) and VIL (max). (See Fig. 5)
This value is for reference only.
If input signal transition time (tT) is longer than 1 ns; [(tT/2) –0.5] ns should be added to tAC (max), tHZ
(max), and tCKSP (min) spec values, [(tT/2) –0.5] ns should be subtracted from tLZ (min), tHZ (min), and
tOH (min) spec values, and (tT –1.0) ns should be added to tCH (min), tCL (min), tSI (min), and tHI (min)
spec values.
tAC also specifies the access time at burst mode.
tAC and tOH are the specs value under OUTPUT LOAD CIRCUIT shown in Fig. 4.
Specified where output buffer is no longer driven.
Actual clock count of tRC (lRC) will be sum of clock count of tRAS (lRAS) and tRP (lRP).
All base values are measured from the clock edge at the command input to the clock edge for the next
command input. All clock counts are calculated by a simple formula: clock count equals base value
divided by clock period (round off to a whole number).
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