MB81F643242C Datasheet, PDF (23/56 Pages) Fujitsu Component Limited. – 4 X 512 K X 32 BIT SYNCHRONOUS DYNAMIC RAM

MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
s BANK OPERATION COMMAND TABLE
MINIMUM CLOCK LATENCY OR DELAY TIME FOR 1 BANK OPERATION
Second
command
(same
bank)
*4
*4
First
command
MRS
tRSC
tRSC
tRSC
tRSC
tRSC
tRSC
tRSC
ACTV
tRCD
tRCD
tRCD
tRCD
tRAS
tRAS
1
READ
*5
*5
*4
*4
1
1
1
1
1
1
1
READA
*1,*2
BL
BL
+
+
tRP
tRP
WRIT
tWR
tWR
1
*4
BL
+
tRP
*4
BL
+
tRP
*2
BL
+
tRP
*2,*7
BL
+
tRP
*4
*4
1
tDPL
tDPL
1
WRITA
PRE
*2
BL-1
+
tDAL
*2,*3
tRP
BL-1
+
tDAL
tRP
*4
BL-1
+
tDAL
*4
BL-1
+
tDAL
*2
BL-1
+
tDAL
*2
BL-1
+
tDAL
*4
*2
*2,*6
1
1
tRP
tRP
1
PALL
*3
tRP
tRP
*6
1
1
tRP
tRP
1
REF
tRC
tRC
tRC
tRC
tRC
tRC
tRC
SELFX
tRC
tRC
tRC
tRC
tRC
tRC
tRC
Notes: *1.
*2.
*3.
*4.
*5.
*6.
*7.
If tRP(min.)<CL×tCK, minimum latency is a sum of (BL+CL)×tCK.
Assume all banks are in Idle state.
Assume output is in High-Z state.
Assume tRAS(min.) is satisfied.
Assume no I/O conflict.
Assume after the last data have been appeared on DQ.
If tRP(min.)<(CL-1)×tCK, minimum latency is a sum of (BL+CL-1)×tCK.
Illegal Command
23