MB81F643242C Datasheet, PDF (19/56 Pages) Fujitsu Component Limited. – 4 X 512 K X 32 BIT SYNCHRONOUS DYNAMIC RAM

MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
PRECHARGE AND PRECHARGE OPTION (PRE, PALL)
SDRAM memory core is the same as conventional DRAMs’, requiring precharge and refresh operations. Precharge
rewrites the bit line and to reset the internal Row address line and is executed by the Precharge command (PRE).
With the Precharge command, SDRAM will automatically be in standby state after precharge time (tRP).
The precharged bank is selected by combination of AP and BA0, BA1 when Precharge command is asserted. If AP
= High, all banks are precharged regardless of BA0, BA1 (PALL). If AP = Low, a bank to be selected by BA0, BA1 is
precharged (PRE).
The auto-precharge enters precharge mode at the end of burst mode of read or write without Precharge command
assertion.
This auto precharge is entered by AP = High when a read or write command is asserted. Refer to “s FUNCTIONAL
TRUTH TABLE”.
AUTO-REFRESH (REF)
Auto-refresh uses the internal refresh address counter. The SDRAM Auto-refresh command (REF) generates
Precharge command internally. All banks of SDRAM should be precharged prior to the Auto-refresh command.
The Auto-refresh command should also be asserted every 16 µs or a total 4096 refresh commands within a 64 ms
period.
SELF-REFRESH ENTRY (SELF)
Self-refresh function provides automatic refresh by an internal timer as well as Auto-refresh and will continue the
refresh function until cancelled by SELFX.
The Self-refresh is entered by applying an Auto-refresh command in conjunction with CKE = Low (SELF). Once
SDRAM enters the self-refresh mode, all inputs except for CKE will be “don’t care” (either logic high or low level
state) and outputs will be in a High-Z state. During a self-refresh mode, CKE = Low should be maintained. SELF
command should only be issued after last read data has been appeared on DQ
Notes: When the burst refresh method is used, a total of 4096 auto-refresh commands within 4 ms must be
asserted prior to the self-refresh mode entry.
SELF-REFRESH EXIT (SELFX)
To exit self-refresh mode, apply minimum tCKSP after CKE brought high, and then the No Operation command (NOP)
or the Deselect command (DESL) should be asserted within one tRC period. CKE should be held High within one
tRC period after tCKSP. Refer to “TIMING DIAGRAM -16” in section “s TIMING DIAGRAMS” for the detail.
It is recommended to assert an Auto-refresh command just after the tRC period to avoid the violation of refresh period.
Notes: When the burst refresh method is used, a total of 4096 auto-refresh commands within 4 ms must be
asserted after the self-refresh exit.
MODE REGISTER SET (MRS)
The mode register of SDRAM provides a variety of different operations. The register consists of four operation
fields; Burst Length, Burst Type, CAS latency, and Operation Code. Refer to “s MODE REGISTER TABLE”.
The mode register can be programmed by the Mode Register Set command (MRS). Each field is set by the address
line. Once a mode register is programmed, the contents of the register will be held until re-programmed by another
MRS command (or part loses power). MRS command should only be issued on condition that all DQ is in Hi-Z.
The condition of the mode register is undefined after the power-up stage. It is required to set each field after
initialization of SDRAM. Refer to “POWER-UP INITIALIZATION” below.
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