MB81F643242C Datasheet, PDF (40/56 Pages) Fujitsu Component Limited. – 4 X 512 K X 32 BIT SYNCHRONOUS DYNAMIC RAM

MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
TIMING DIAGRAM – 10 : WRITE INTERRUPTED BY PRECHARGE (EXAMPLE @ CL = 3)
CLK
Command
PRECHARGE
tDPL (min)
tRP (min)
ACTV
DQ0 to DQ31
DATA-
LAST
DATA-IN
MASKED
by Precharge
Note: The precharge command (PRE) should only be issued after the tDPL of final data input is satisfied.
PRECHARGE means ’ PRE’ or ’PALL’.
TIMING DIAGRAM – 11 : READ INTERRUPTED BY WRITE (EXAMPLE @ CL = 3, BL = 4)
CLK
Command
READ
IOWD (2 clocks)
WRIT
DQM
(DQM0 to DQM3)
DQ0 to DQ31
*1
*2
*3
IDQZ (2 clocks)
Q1
Masked
IDWD (same clock)
D1
D2
Notes: *1. First DQM makes high-impedance state High-Z between last output and first input data.
*2. Second DQM makes internal output data mask to avoid bus contention.
*3. Third DQM in illustrated above also makes internal output data mask. If burst read ends (final data output) at or after the
second clock of burst write, this third DQM is required to avoid internal bus contention.
40