MB81F643242C Datasheet, PDF (20/56 Pages) Fujitsu Component Limited. – 4 X 512 K X 32 BIT SYNCHRONOUS DYNAMIC RAM

MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
POWER-UP INITIALIZATION
The SDRAM internal condition after power-up will be undefined. It is required to follow the following Power On
Sequence to execute read or write operation.
1. Apply power and start clock. Attempt to maintain either NOP or DESL command at the input.
2. Maintain stable power, stable clock, and NOP condition for a minimum of 100 µs.
3. Precharge all banks by Precharge (PRE) or Precharge All command (PALL).
4. Assert minimum of 2 Auto-refresh command (REF).
5. Program the mode register by Mode Register Set command (MRS).
In addition, it is recommended DQM and CKE to track VCC to insure that output is High-Z state. The Mode Register
Set command (MRS) can be set before 2 Auto-refresh command (REF).
20