MB81F643242C Datasheet, PDF (25/56 Pages) Fujitsu Component Limited. – 4 X 512 K X 32 BIT SYNCHRONOUS DYNAMIC RAM

MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
s MODE REGISTER TABLE
MODE REGISTER SET
BA1 BA0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ADDRESS
*3
*3
0
0
0
Op-
code
0
0
CL
BT
BL
MODE
REGISTER
A6 A5 A4 CAS Latency
0 0 0 Reserved
0 0 1 Reserved
010
2
011
3
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Reserved
1 1 1 Reserved
A2
A1
A0
Burst Length
BT = 0
BT = 1 ^*2
000
1
001
2
010
4
011
8
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Reserved
1 1 1 Full Column
Reserved
2
4
8
Reserved
Reserved
Reserved
Reserved
A9
Op-code
0 Burst Read & Burst Write
1 Burst Read & Single Write ^*1
A3
Burst Type
0
Sequential (Wrap round, Binary-up)
1
Interleave (Wrap round, Binary-up)
Notes: *1. When A9 = 1, burst length at Write is always one regardless of BL value.
*2. BL = 1 and Full Column are not applicable to the interleave mode.
*3. A7 = 1 and A8 = 1 are reserved for vender test.
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