MB81F643242C Datasheet, PDF (41/56 Pages) Fujitsu Component Limited. – 4 X 512 K X 32 BIT SYNCHRONOUS DYNAMIC RAM

MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
TIMING DIAGRAM – 12 : WRITE TO READ TIMING (EXAMPLE @ CL = 3, BL = 4)
CLK
Command
WRIT
tWR (min)
READ
DQM
(DQM0 to DQM3)
DQ0 to DQ31
(CL-1) × tCK
D3
D1
D2
Masked
by READ
Note: Read command should be issued after tWR of final data input is satisfied.
tAC (max)
Q1
Q2
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