MC68HC705J1ACPE Datasheet, PDF (99/162 Pages) Freescale Semiconductor, Inc – Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.
Computer Operating Properly (COP) Module
Interrupts
Clearing the COP bit disables the COP watchdog timer regardless of the
IRQ/V_PP pin voltage.
If the main program executes within the COP timeout period, the clearing
routine should be executed only once. If the main program takes longer
than the COP timeout period, the clearing routine must be executed
more than once.
NOTE:
Place the clearing routine in the main program and not in an interrupt
routine. Clearing the COP watchdog in an interrupt routine might prevent
COP watchdog timeouts even though the main program is not operating
properly.
7.4 Interrupts
The COP watchdog does not generate interrupts.
7.5 COP Register
The COP register (COPR) is a write-only register that returns the
contents of EPROM location $07F0 when read.
Address: $07F0
Bit 7
6
5
4
3
2
Read:
Write:
Reset:
= Unimplemented
Figure 7-1. COP Register (COPR)
1
Bit 0
COPC
0
COPC — COP Clear Bit
This write-only bit resets the COP watchdog. Reading address $07F0
returns undefined results.
MC68HC705J1A — Rev. 4.0
Computer Operating Properly (COP) Module
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Technical Data