MC68HC705J1ACPE Datasheet, PDF (64/162 Pages) Freescale Semiconductor, Inc – Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
Source
Form
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
MUL
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
NOP
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
Table 3-6. Instruction Set Summary (Sheet 4 of 6)
Operation
Unconditional Jump
Jump to Subroutine
Load Accumulator with Memory Byte
Load Index Register with Memory Byte
Logical Shift Left (Same as ASL)
Logical Shift Right
Description
Effect
on CCR
H I NZC
PC ← Jump Address
—————
DIR
EXT
IX2
IX1
IX
BC dd 2
CC ^{hh ll} 3
DC ee ff 4
EC ff 3
FC
2
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Effective Address
—————
DIR
EXT
IX2
IX1
IX
BD ^dd 5
CD hh ll 6
DD ee ff 7
ED ^ff 6
FD
5
A ← (M)
IMM A6 ii 2
DIR B6 dd 3
——   —
EXT
IX2
C6 ^{hh ll} 4
D6 ee ff 5
IX1 E6 ff 4
IX F6
3
X ← (M)
IMM AE ⁱⁱ 2
DIR BE dd 3
——   —
EXT
IX2
CE hh ll 4
DE ^{ee ff} 5
IX1 EE ff 4
IX FE
3
C
b7
0
b0
DIR 38 ^dd 5
INH 48
3
— —    INH 58
3
IX1 68 ff 6
IX 78
5
0
b7
C
b0
DIR 34 ^dd 5
INH 44
3
— — 0   INH 54
3
IX1 64 ff 6
IX 74
5
Unsigned Multiply
Negate Byte (Two’s Complement)
No Operation
Logical OR Accumulator with Memory
X : A ← (X) × (A)
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
A ← (A) ∨ (M)
0 — — — 0 INH 42
11
DIR 30 ^dd 5
INH 40
3
— —    INH 50
3
IX1 60 ff 6
IX 70
5
— — — — — INH 9D
2
IMM AA ii 2
DIR BA ^dd 3
——   —
EXT
IX2
CA hh ll 4
DA ee ff 5
IX1 EA ^ff 4
IX FA
3
Technical Data
MC68HC705J1A — Rev. 4.0
Central Processor Unit (CPU)
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